Photomasks are becoming an increasingly expensive fraction of the overall semiconductor manufacture cost. Traditionally, photomasks have accounted for less than one percent of the cost of semiconductor chip manufacturing. However, as photomask technology requirements become more advanced and volume per part number decreases, the relative cost of photomask fabrication is increasing significantly.
One of the most costly photomask production steps is forming the image in a photoresist by using energized radiation, such as e-beam or laser direct write systems. The increasingly stringent requirements on photomask performance have necessitated the use of more advanced technologies, including vector shaped beam e-beam lithography. In the vector shaped beam lithography technology, the photomask lithography step can take eight to ten hours and as much as twenty four or thirty six hours, depending on the pattern complexity.
The throughput of photomask patterning is directly related to the number of exposure “shots” (discrete exposure regions) used to construct the desired image. Current design, optical proximity correction (OPC), and use of fill shapes are all done with little regard for the parameter of number of shots required for shape reconstruction. Similarly modern chip design's increased usage of “dummy” features, such as fill shapes, holes, and gate array like patterns, leads to increased photomask complexity and costs from increased print-time. The function of these patterns is to increase pattern density and geometric homogeneity which help achieve tolerance requirements during photomask and wafer fabrication.